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M
* PIC12CE673 * PIC12CE674
PIC12CE67X
Pin Diagram:
PDIP, Windowed CERDIP
VDD GP5/OSC1/CLKIN GP4/OSC2/AN3/CLKOUT GP3/MCLR/VPP
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
Devices Included in this Data Sheet:
High-Performance RISC CPU:
* Only 35 single word instructions to learn * All instructions are single cycle (400 ns) except for program branches which are two-cycle * Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle Memory Device Program PIC12CE673 1024 x 14 PIC12CE674 2048 x 14 * * * * * * Data RAM 128 x 8 128 x 8 Data EEPROM 16 x 8 16 x 8
1 2 3 4
8 7 6 5
VSS GP0/AN0 GP1/AN1/VREF GP2/T0CKI/AN2/INT
Special Microcontroller Features:
* In-Circuit Serial Programming (ICSPTM) * Internal 4 MHz oscillator with programmable calibration * Selectable clockout * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Internal pull-ups on I/O pins (GP0, GP1, GP3) * Internal pull-up on MCLR pin * Selectable oscillator options: - INTRC: Precision internal 4 MHz oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal
PIC12CE673 PIC12CE674
14-bit wide instructions 8-bit wide data path Interrupt capability Special function hardware registers 8-level deep hardware stack Direct, indirect and relative addressing modes for data and instructions
Peripheral Features:
* Four-channel, 8-bit A/D converter * 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler * Interrupt on pin change (GP0, GP1, GP3) * 1,000,000 erase/write cycle EEPROM data memory * EEPROM data retention > 40 years
CMOS Technology:
* Low-power, high-speed CMOS EPROM/ EEPROM technology * Fully static design * Wide operating voltage range 2.5V to 5.5V * Commercial, Industrial, and Extended temperature ranges * Low power consumption < 2 mA @ 5V, 4 MHz 15 A typical @ 3V, 32 kHz < 1 A typical standby current
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 1
PIC12CE67X
Table of Contents
1.0 General Description ....................................................................................................................................................................... 3 2.0 PIC12CE67X Device Varieties....................................................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................................................... 7 4.0 Memory Organization................................................................................................................................................................... 11 5.0 I/O Port......................................................................................................................................................................................... 25 6.0 EEPROM Peripheral Operation ................................................................................................................................................... 27 7.0 Timer0 Module ............................................................................................................................................................................. 31 8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................... 37 9.0 Special Features of the CPU ....................................................................................................................................................... 45 10.0 Instruction Set Summary.............................................................................................................................................................. 61 11.0 Development Support .................................................................................................................................................................. 75 12.0 Electrical Characteristics for PIC12CE67X .................................................................................................................................. 81 13.0 DC and AC Characteristics - PIC12CE67X ................................................................................................................................. 99 14.0 Packaging Information ............................................................................................................................................................... 103 Index .................................................................................................................................................................................................. 107 PIC12CE67X Product Identification System ..................................................................................................................................... 113
To Our Valued Customers
Most Current Data Sheet
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
DS40181B-page 2
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
1.0 GENERAL DESCRIPTION
The PIC12CE67X devices are low-cost, high-performance, CMOS, fully-static, 8-bit microcontroller with integrated analog-to-digital (A/D) converter and EEPROM data memory in the PIC12CEXXX Microcontroller family. All PICmicroTM microcontrollers employ an advanced RISC architecture. The PIC12C67X microcontrollers have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC12C67X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC12CE67X devices have 128 bytes of RAM, 16 bytes of EEPROM data memory, 5 I/O pins and 1 input pin. In addition a timer/counter is available. Also a 4channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring lowcost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC12CE67X device has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. The Power-On Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) eliminate the need for external reset circuitry. There are five oscillator configurations to choose from, including INTRC precision internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability.The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable windowed package version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers while benefiting from the OTP's flexibility. The PIC12CE67X device fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC12CE67X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, communications and coprocessor applications).
1.1
Family and Upward Compatibility
The PIC12CE67X products are compatible with other members of the 14-Bit, PIC12C67X and PIC16CXXX families.
1.2
Development Support
The PIC12CE67X device is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also available.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 3
PIC12CE67X
TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 Maximum Frequency of Operation (MHz) EPROM Program Memory RAM Data Memory (bytes) 4 4 4 4 10 PIC12C672 PIC12CE673 PIC12CE674 10 10 10
Clock
512 x 12
1024 x 12
512 x 12
1024 x 12
1024 x 14
2048 x 14
1024 x 14
2048 x 14
Memory
25
41
25
41
128
128
128
128
EEPROM -- Data Memory (bytes) Peripherals Timer Module(s) A/D Converter (8-bit) Channels Wake-up from SLEEP on pin change Interrupt Sources Features I/O Pins Input Pins Internal Pull-ups TMR0 --
--
16
16
--
--
16
16
TMR0 --
TMR0 --
TMR0 --
TMR0 4
TMR0 4
TMR0 4
TMR0 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-- 5 1 Yes
-- 5 1 Yes Yes
-- 5 1 Yes Yes
-- 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
In-Circuit Yes Serial Programming Number of Instructions Packages 33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
35 8-pin DIP, JW, SOIC
35 8-pin DIP, JW, SOIC
35 8-pin DIP, JW
35 8-pin DIP, JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
DS40181B-page 4
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
2.0 PIC12CE67X DEVICE VARIETIES
2.3 Quick-Turn-Programming (QTP) Devices
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC12CE67X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For example, the PIC12CE67X device "type" is indicated in the device number: 1. CE, as in PIC12CE674. These devices have OTP program memory, EEPROM data memory and operate over the standard voltage range.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn Programming (SQTPSM) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in windowed package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Microchip's PICSTART(R) Plus and PRO MATE(R) programmers both support the PIC12CE67X. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 5
PIC12CE67X
NOTES:
DS40181B-page 6
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12CE67X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12CE67X uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses also allow instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (400 ns @ 10 MHz) except for program branches. The table below lists program memory (EPROM), data memory (RAM), and non-volatile memory (EEPROM) for each PIC12CE67X device. Device PIC12CE673 PIC12CE674 Program Memory 1K x 14 2K x 14 RAM Data Memory 128 x 8 128 x 8 EEPROM Data Memory 16x8 16x8 The PIC12CE67X can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC12CE67X has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC12CE67X simple yet efficient. In addition, the learning curve is reduced significantly. PIC12CE67X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 7
PIC12CE67X
FIGURE 3-1: PIC12CE67X BLOCK DIAGRAM
Device PIC12CE673 PIC12CE674
Program Memory 1K x 14 2K x 14
Data Memory (RAM) 128 x 8 128 x 8
Non-Volatile Memory (EEPROM) 16 x 8 16 x 8
13 Program Counter EPROM Program Memory
Data Bus
8
GPIO GP0/AN0 GP1/AN1/VREF GP2/T0CKI/AN2/INT GP3/MCLR/Vpp GP4/OSC2/AN3/CLKOUT GP5/OSC1/CLKIN SCL SDA
8 Level Stack (13 bit)
RAM 128 bytes File Registers RAM Addr (1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg
16x8 EEPROM Data Memory
8 3
Power-up Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Internal 4 MHz Clock Timing Generation Oscillator Start-up Timer Watchdog Timer Power-on Reset 8
MUX
ALU
W reg
MCLR VDD, VSS
Timer0
A/D
Note 1: Higher order bits are from the STATUS register.
DS40181B-page 8
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
TABLE 3-1:
Name GP0/AN0
PIC12CE67X PINOUT DESCRIPTION
DIP Pin # 7 I/O/P Type I/O Buffer Type TTL/ST Description Bi-directional I/O port/serial programming data/analog input 0. Can be software programmed for internal weak pull-up and interrupt on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. Bi-directional I/O port/serial programming clock/analog input 1/voltage reference. Can be software programmed for internal weak pull-up and interrupt on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. Bi-directional I/O port/analog input 2. Can be configured as T0CKI or external interrupt. Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and interrupt on pin change. Weak pull-up always on if configured as MCLR . This buffer is Schmitt Trigger when in MCLR mode. Bi-directional I/O port/oscillator crystal output/analog input 3. Connections to crystal or resonator in crystal oscillator mode (HS, XT and LP modes only, GPIO in other modes). In EXTRC and INTRC modes, the pin output can be configured to CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Bidirectional IO port/oscillator crystal input/external clock source input (GPIO in INTRC mode only, OSC1 in all other oscillator modes). Schmitt trigger in EXTRC mode only. Positive supply for logic and I/O pins Ground reference for logic and I/O pins
GP1/AN1/VREF
6
I/O
TTL/ST
GP2/T0CKI/AN2/INT GP3/MCLR/VPP
5 4
I/O I
ST TTL/ST
GP4/OSC2/AN3/ CLKOUT
3
I/O
TTL
GP5/OSC1/CLKIN
2
I/O
TTL/ST
VDD VSS
1 8
P P
-- --
Legend: I = input, O = output, I/O = input/output, P = power, -- = not used, TTL = TTL input, ST = Schmitt Trigger input
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 9
PIC12CE67X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (EXTRC and INTRC modes)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h 2. MOVWF GPIO 3. CALL 4. BSF SUB_1
Fetch 1
GPIO, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40181B-page 10
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
4.2
Data Memory Organization
The PIC12CE67X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC12CE673 the first 1K x 14 (0000h-03FFh) is implemented. For the PIC12CE674, the first 2K x 14 (0000h-07FFh) is implemented. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit. RP0 (STATUS<5>) = 1 Bank 1 RP0 (STATUS<5>) = 0 Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access. Also note that F0h through FFh on the PIC12CE67X is mapped into Bank 0 registers 70h-7Fh as common RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE
FIGURE 4-1:
PIC12CE67X PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).
Stack Level 8 Reset Vector
0000h
Peripheral Interrupt Vector
0004h 0005h
On-chip Program Memory (PIC12CE674 only)
03FFh 0400h 07FFh 0800h
1FFFh
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 11
PIC12CE67X
FIGURE 4-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR GPIO INDF(1) OPTION PCL STATUS FSR TRIS
PIC12CE67X REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
PCLATH INTCON PIR1
PCLATH INTCON PIE1 PCON OSCCAL
ADRES ADCON0
ADCON1 General Purpose Register
General Purpose Register 70h 7Fh Bank 0 Mapped in Bank 0 Bank 1
BFh C0h EFh F0h FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS40181B-page 12
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
TABLE 4-1:
Address Name
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets(3)
Bank 0 00h(1) 01h 02h(1) 03h
(1)
INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADRES ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP
(4)
0000 0000 xxxx xxxx 0000 0000
0000 0000 uuuu uuuu 0000 0000 000q quuu uuuu uuuu 11uu uuuu -- -- -- -- ---0 0000 0000 000u -0-- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- uuuu uuuu 0000 0000
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx xxxx xxxx
04h(1) 05h 06h 07h 08h 09h 0Ah(1,2) 0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Indirect data memory address pointer SCL SDA GP5 GP4 GP3 GP2 GP1 GP0
11xx xxxx -- -- -- --
Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- GPIE -- T0IF -- INTF -- GPIF --
---0 0000 0000 000x -0-- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- xxxx xxxx
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON
0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 13
PIC12CE67X
TABLE 4-1:
Address Name
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets(3)
Bank 1 80h(1) 81h 82h(1) 83h(1) 84h(1) 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION PCL STATUS FSR TRIS -- -- -- -- PCLATH INTCON PIE1 -- PCON OSCCAL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx 0011 1111 -- -- -- -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the PC INTE -- GPIE -- T0IF -- INTF -- GPIF -- ---0 0000 0000 000x -0-- ----- -- CAL4 -- CAL3 -- CAL2 -- CAL1 -- CAL0 POR -- -- -- ---- --01000 00--- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCFG2 PCFG1 PCFG0 ---- -000 0000 0000 1111 1111 0000 0000 000q quuu uuuu uuuu 0011 1111 -- -- -- -- ---0 0000 0000 000u -0-- ----- ---- --uuuuu uu--- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ---- -000
Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO
Indirect data memory address pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- -- GPIO Data Direction Register
Unimplemented -- CAL5
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented --
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
DS40181B-page 14
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12CE67X and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 4-3:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
Reserved Reserved IRP RP1 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 15
PIC12CE67X
4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on GPIO. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).
FIGURE 4-4:
R/W-1 GPPU bit7
OPTION REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GPPU: Weak pullup enable 1 = Weak pullups disabled 0 = Weak pullups enabled (GP0, GP1, GP3) INTEDG: Interrupt edge 1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin 0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI/AN2/INT pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin 0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, GPIO Port change and External GP2/INT Pin interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-x GPIF bit0
R/W-0 PEIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: INT External Interrupt Enable bit 1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin 0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin GPIE: GPIO Interrupt on Change Enable bit 1 = Enables the GPIO Interrupt on Change 0 = Disables the GPIO Interrupt on Change T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: INT External Interrupt Flag bit 1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software) 0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur GPIF: GPIO Interrupt on Change Flag bit 1 = GP0, GP1, or GP3 pins changed state (must be cleared in software) 0 = Neither GP0, GP1, nor GP3 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 17
PIC12CE67X
4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the Peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
FIGURE 4-6:
U-0 -- bit7
PIE1 REGISTER (ADDRESS 8Ch)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R/W-0 ADIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt
bit 5-0: Unimplemented: Read as '0'
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-7:
U-0 -- bit7
PIR1 REGISTER (ADDRESS 0Ch)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R/W-0 ADIF
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete
bit 5-0: Unimplemented: Read as '0'
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 19
PIC12CE67X
4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), an external MCLR Reset, and WDT Reset.
FIGURE 4-8:
U-0 -- bit7
PCON REGISTER (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR U-0 -- bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) Unimplemented: Read as '0'
bit 0:
DS40181B-page 20
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.7 OSCCAL REGISTER The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration. Increasing the cal value increases the frequency.
FIGURE 4-9:
R/W-1 CAL5 bit7
OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 -- U-0 -- bit0
R/W-0 CAL4
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented, read as 0
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 21
PIC12CE67X
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-10 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC12C67X family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
FIGURE 4-10: LOADING OF PC IN DIFFERENT SITUATIONS
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0 Instruction with PCL as Destination ALU result
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.4
Program Memory Paging
4.3.1
COMPUTED GOTO
The PIC12CE67X ignores both paging bits PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC12CE67X is not recommended since this may affect upward compatibility with future products.
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
DS40181B-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
4.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-1:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-11. However, IRP is not used in the PIC12CE67X. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1.
NEXT
CONTINUE
FIGURE 4-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)RP1
Indirect Addressing
0 IRP
(1)
RP0
6
from opcode
7
FSR register
0
bank select
location select 00 00h 01 10 11
bank select 180h
location select
not used Data Memory
7Fh
1FFh
Bank 0 For register file map detail see Figure 4-2.
Bank 1
Bank 2
Bank 3
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 23
PIC12CE67X
NOTES:
DS40181B-page 24
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
5.0 I/O PORT
As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. Port pins GP6 and GP7 are used for the serial EEPROM interface. These port pins are not available externally on the package. Users should avoid writing to pins GP6 and GP7 when not communicating with the serial EEPROM memory. Please see section 6.0, EEPROM Peripheral Operation, for information on serial EEPROM communication.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 6 and 7 (SDA and SCL) are used by the EEPROM peripheral. Refer to Section 6.0 and Appendix A for use of SDA and SCL. Please note that GP3 is an input only pin. The configuration word can set several I/O's to alternate functions. When acting as alternate functions the pins will read as `0' during port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with interrupt on change. The interrupt on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, the weak pull-up is always on. Interrupt on change for this pin is not set and GP3 will read as '0'. Interrupt on change is enabled by setting INTCON<3>. Note that external oscillator use overrides the GPIO functions on GP4 and GP5.
Note:
On a Power-on Reset, GP0, GP1, GP2, GP4 are configured as analog inputs and read as '0'.
FIGURE 5-1:
Data Bus D WR Port
EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Q Data Latch VDD Q P
CK
5.2
TRIS Register
W Reg N D TRIS Latch TRIS `f' CK Q Q VSS I/O pin(1)
This register controls the data direction for GPIO. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and its TRIS bit will always read as '1'. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
Reset
RD Port Note 1: I/O pins have protection diodes to VDD and VSS. GP3 is input only with no data latch and no output drivers.
Upon reset, the TRIS register is all '1's, making all pins inputs. TRIS for pins GP4 and GP5 is forced to a 1 where appropriate. Writes to TRIS <5:4> will have an effect in EXTRC and INTRC oscillator modes only. When GP4 is configured as CLKOUT, changes to TRIS<4> will have no effect.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 5-2. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are nonlatching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 25
PIC12CE67X
TABLE 5-1: SUMMARY OF PORT REGISTERS
Value on Power-on Reset --11 1111 PS1 DC GP1 PS0 C GP0 1111 1111 0001 1xxx 11xx xxxx Value on all other Resets --11 1111 1111 1111 000q quuu 11uu uuuu
Address 85h 81h 03h 05h
Name TRIS OPTION STATUS GPIO
Bit 7 -- GPPU IRP
(1)
Bit 6 -- INTEDG RP1
(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO Data Direction Register T0CS RP0 GP5 T0SE TO GP4 PSA PD GP3 PS2 Z GP2
SCL
SDA
Legend: Shaded cells not used by Port Registers, read as `0', -- = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 9.4 for possible values. Note 1: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
5.4
5.4.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
Example 5-1 shows the effect of two sequential readmodify-write instructions on an I/O port.
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU. Then the BSF operation takes place on bit5 and GPIO is written to the output latches. If another bit of GPIO is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ---------- ---------BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
FIGURE 5-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched GP5:GP0 Port pin written here Instruction executed MOVWF GPIO (Write to GPIO) Port pin sampled here MOVF GPIO,W (Read GPIO) NOP MOVWF GPIO PC + 1 MOVF GPIO,W PC + 2 NOP PC + 3 NOP
This example shows a write to GPIO followed by a read from GPIO. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40181B-page 26
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
6.0 EEPROM PERIPHERAL OPERATION
* Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 6-1). 6.1.1 BUS NOT BUSY (A)
The PIC12CE673 and PIC12CE674 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 that are connected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W
Both data and clock lines remain HIGH. 6.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 6.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 6.1.4 DATA VALID (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the processor device and is theoretically unlimited. 6.1.5 ACKNOWLEDGE
The code for these functions is available on our web site (www.microchip.com). The code will be accessed by either including the source code FL67XINC.ASM or by linking FLASH67X.ASM. FLASH62.IMC provides external definition to the calling program. 6.0.1 SERIAL DATA
SDA is a bi-directional pin used to transfer addresses and data into and data out of the device. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 6.0.2 SERIAL CLOCK
The EEPROM, when addressed, will generate an acknowledge after the reception of each byte. The processor must generate an extra clock pulse which is associated with this acknowledge bit. Note: Acknowledge bits are not generated if an internal programming cycle is in progress.
This SCL input is used to synchronize the data transfer from and to the EEPROM.
6.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the EEPROM data memory. In this section, the term "processor" is used to denote the portion of the PIC12CE67X that interfaces to the EEPROM via software.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. The processor must signal an end of data to the EEPROM by not generating an acknowledge bit on the last byte that has been clocked out of the EEPROM. In this case, the EEPROM must leave the data line HIGH to enable the processor to generate the STOP condition (Figure 6-2).
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 27
PIC12CE67X
FIGURE 6-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(C) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
FIGURE 6-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL SDA
1
2
3
4
5
6
7
8
9
1
2
3
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
6.2
Device Addressing
FIGURE 6-3:
CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor transmits a control byte consisting of a EEPROM address and a Read/Write bit that indicates what type of operation is to be performed. The EEPROM address consists of a 4-bit device code (1010) followed by three don't care bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 6-3). The bus is monitored for its corresponding EEPROM address all the time. It generates an acknowledge bit if the EEPROM address was true and it is not in a programming mode.
Device Select Bits
Don't Care Bits 0 X X X R/W ACK
S
1
0
1
EEPROM Address Start Bit Acknowledge Bit
DS40181B-page 28
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
6.3
6.3.1
WRITE OPERATIONS
BYTE WRITE
6.4
ACKNOWLEDGE POLLING
Following the start signal from the processor, the device code (4 bits), the don't care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the processor. This indicates to the addressed EEPROM that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the processor is the word address and will be written into the address pointer. Only the lower four address bits are used by the device, and the upper four bits are don't cares. The address byte is acknowledgeable and the processor will then transmit the data word to be written into the addressed memory location. The memory acknowledges again and the processor generates a stop condition. This initiates the internal write cycle, and during this time will not generate acknowledge signals (Figure 6-5). After a byte write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abort and no data will be written. The EEPROM memory employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below minimum VDD. Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both SDA and SCL are held high.
Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the processor, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the processor sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the processor can then proceed with the next read or write command. See Figure 6-4 for flow diagram.
FIGURE 6-4:
ACKNOWLEDGE POLLING FLOW
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did EEPROM Acknowledge (ACK = 0)? YES Next Operation
NO
FIGURE 6-5:
BUS ACTIVITY PROCESSOR SDA LINE
BYTE WRITE
S T A R T S 1 0 1 CONTROL BYTE WORD ADDRESS DATA S T O P P A C K A C K
0
X
X
X
0 A C K
X
X
X
X
BUS ACTIVITY X = Don't Care Bit
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6.5 READ OPERATIONS
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the EEPROM address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.5.1 CURRENT ADDRESS READ EEPROM as part of a write operation. After the word address is sent, the processor generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the processor issues the control byte again but with the R/W bit set to a one. It will then issue an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-7). After this command, the internal address counter will point to the address location following the one that was just read. 6.5.3 SEQUENTIAL READ
It contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the EEPROM address with the R/W bit set to one, the EEPROM issues an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-6). 6.5.2 RANDOM READ
Sequential reads are initiated in the same way as a random read except that after the device transmits the first data byte, the processor issues an acknowledge as opposed to a stop condition in a random read. This directs the EEPROM to transmit the next sequentially addressed 8-bit word (Figure 6-8). To provide sequential reads, it contains an internal address pointer which is incremented by one at the completion of each read operation. This address pointer allows the entire memory contents to be serially read during one operation.
Random read operations allow the processor to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the
FIGURE 6-6:
CURRENT ADDRESS READ
BUS ACTIVITY PROCESSOR SDA LINE BUS ACTIVITY S T A R T CONTROL BYTE S T O P
S 1 0 1 0 XXX 1
P
A C K DATA N O A C K
X = Don't Care Bit
FIGURE 6-7:
RANDOM READ
S T A R T CONTROL BYTE WORD ADDRESS (n)
XXXX
BUS ACTIVITY PROCESSOR
S T A R T
CONTROL BYTE
S T O P
S 10 10XXX0
S 10 10XXX1
P
A C K DATA (n) N O A C K
SDA LINE
BUS ACTIVITY
X = Don't Care Bit
A C K
A C K
FIGURE 6-8:
BUS ACTIVITY PROCESSOR SDA LINE BUS ACTIVITY
SEQUENTIAL READ
CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P
P
A C K A C K A C K A C K N O A C K
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7.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing
7.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 74 for Timer0 interrupt timing.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 TCY delay) TMR0 PSout 8
GP2/T0CKI/ AN2/INT
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
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FIGURE 7-3:
PC (Program Counter) Instruction Fetch TMR0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 7-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) Timer0 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 3Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
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7.2 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.2.2 TMR0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres-
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
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7.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
FIGURE 7-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 GP2/T0CKI/ AN2/INT 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
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7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 7-2.
EXAMPLE 7-2:
CLRWDT BSF MOVLW MOVWF BCF
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler STATUS, RP0 ;Bank 1 b'xxxx0xxx' ;Select TMR0, new ;prescale value and OPTION_REG ;clock source STATUS, RP0 ;Bank 0
EXAMPLE 7-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear TMR0 & Prescaler ;Bank 1 ;Clears WDT ;Select new prescale ;value & WDT ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION_REG STATUS, RP0
TABLE 7-1:
Address Name 01h 0Bh/8Bh 81h 85h TMR0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR xxxx xxxx INTE T0SE TRIS4 GPIE PSA TRIS3 T0IF PS2 TRIS2 INTF PS1 TRIS1 GPIF PS0 TRIS0 0000 000x 1111 1111 --11 1111 Value on all other Resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS TRIS5
INTCON
OPTION GPPU INTEDG TRIS -- --
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
(c) 1998 Microchip Technology Inc.
Preliminary
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NOTES:
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8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The ADCON0 register, shown in Figure 8-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 8-2, configures the functions of the port pins. The port pins can be configured as analog inputs (GP1 can also be a voltage reference) or as digital I/O. Note: If the port pins are configured as analog inputs (reset condition), reading the port (MOVF GP,W) results in reading '0's. Changing ADCON1 register can cause the GPIF and INTF flags to be set in the INTCON register. These interrupts should be disabled prior to modifying ADCON1.
The analog-to-digital (A/D) converter module has four analog inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the GP1/AN1/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1)
Note:
FIGURE 8-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 r R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 r R/W-0 ADON bit0
R/W-0 R/W-0 ADCS1 ADCS0 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Reserved bit 4-3: CHS1:CHS0: Analog Channel Select bits 00 = channel 0, (GP0/AN0) 01 = channel 1, (GP1/AN1) 10 = channel 2, (GP2/AN2) 11 = channel 3, (GP4/AN3) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: bit 0: Reserved ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current
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Preliminary
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FIGURE 8-2:
U-0 -- bit7
ADCON1 REGISTER (ADDRESS 9Fh)
U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0
U-0 --
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000(1) 001 010 011 100 101 110 111 A = Analog input D = Digital I/O Note 1: Value on reset. Note 2: Any instruction that reads a pin configured as an analog input will read a '0'. A A D D D D D D GP4 A A A A D D D D GP2 A VREF A VREF A VREF D D GP1 A A A A A A A D GP0 VREF VDD GP1 VDD GP1 VDD GP1 VDD VDD
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The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF (PIE1<6>) is set. The block diagrams of the A/D module are shown in Figure 8-3. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine sample time, see Section 8.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 8-3:
A/D BLOCK DIAGRAM
CHS1:CHS0
11 VIN (Input voltage) 10
GP4/AN3 GP2/AN2
A/D Converter
01 GP1/AN1/VREF 00 VDD VREF (Reference voltage) PCFG2:PCFG0 000 010 100 110 001 011 101 or or or or or or GP0/AN0
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Preliminary
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8.1 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 8-4. The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 81 may be used. This equation assumes that 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. Note 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. Note 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 8-1:
CALCULATING THE MINIMUM REQUIRED SAMPLE TIME
EQUATION 8-1:
A/D MINIMUM CHARGING TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 s + Tc + [(Temp - 25C)(0.05 s/C)] TC = -CHOLD (RIC + RSS + RS) ln(1/512) -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) -51.2 pF (18 k) ln(0.0020) -0.921 s (-6.2146) 5.724 s TACQ = 5 s + 5.724 s + [(50C - 25C)(0.05 s/C)] 10.724 s + 1.25 s 11.974 s
VHOLD = (VREF - (VREF/512)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) or Tc = -(51.2 pF)(1 k + RSS + RS) ln(1/511)
Example 8-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following system assumptions. Rs = 10 k 1/2 LSb error VDD = 5V Rss = 7 k Temp (system max.) = 50C VHOLD = 0 @ t = 0
FIGURE 8-4:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
Rs
RAx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
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8.2 Selecting the A/D Conversion Clock 8.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal ADC RC oscillator The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channel will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN3:AN0 pins), may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 8-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 8-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Device Frequency 4 MHz 500 2.0 s 8.0 s ns(2) 1.25 MHz 1.6 s 6.4 s 25.6 s(3) 333.33 kHz 6 s 24 s(3) 96 s(3)
Operation 2TOSC 8TOSC 32TOSC
ADCS1:ADCS0 00 01 10
11 Internal ADC RC Oscillator(5) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1) Note 1: The RC source has a typical TAD time of 4 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification. 5: For extended voltage devices (LC), please refer to Electrical Specifications section.
(c) 1998 Microchip Technology Inc.
Preliminary
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8.4 A/D Conversions
Example 8-2 show how to perform an A/D conversion. The GP pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the GP0 channel. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel.
EXAMPLE 8-2:
BSF CLRF BSF BCF MOVLW MOVWF BCF BSF BSF ; ; ; ;
DOING AN A/D CONVERSION
RP0 ADIE RP0 ; ; ; ; ; ; ; ; ; Select Page 1 Configure A/D inputs Enable A/D interrupts Select Page 0 RC Clock, A/D is on, Channel 0 is selected Clear A/D interrupt flag bit Enable peripheral interrupts Enable all interrupts
STATUS, ADCON1 PIE1, STATUS, 0xC1 ADCON0 PIR1, INTCON, INTCON,
ADIF PEIE GIE
Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0, GO ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion.
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PIC12CE67X
8.5 A/D Operation During Sleep 8.7 Effects of a RESET
The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, the GO/DONE bit must be set, followed by the SLEEP instruction. A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a Reset. The ADRES register will contain unknown data after a Power-on Reset.
8.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. Note: For the PIC12CE67X, care must be taken when using the GP4 pin in A/D conversions due to its proximity to the OSC1 pin.
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
8.9
Transfer Function
8.6
A/D Accuracy/Error
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is 1 LSb (or Analog VREF / 256) (Figure 8-5).
Digital code output
The overall accuracy of the A/D is less than 1 LSb for VDD = 5V 10% and the analog VREF = VDD. This overall accuracy includes offset error, full scale error, and integral error. The A/D converter is guaranteed to be monotonic. The resolution and accuracy may be less when either the analog reference (VDD) is less than 5.0V or when the analog reference (VREF) is less than VDD. The maximum pin leakage current is 5 A. In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy.
FIGURE 8-5:
A/D TRANSFER FUNCTION
FFh FEh
04h 03h 02h 01h 00h 256 LSb (full scale) 255 LSb 0.5 LSb 1 LSb 2 LSb 3 LSb 4 LSb
Analog input voltage
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 43
PIC12CE67X
FIGURE 8-6:
ADON = 0
FLOWCHART OF A/D OPERATION
Yes ADON = 0?
No Acquire Selected Channel
Yes GO = 0?
No
A/D Clock = RC? No
Yes
Start of A/D Conversion Delayed 1 Instruction Cycle
SLEEP Yes Instruction? No
Finish Conversion GO = 0 ADIF = 1
Device in SLEEP? No
Yes
Abort Conversion GO = 0 ADIF = 0
Finish Conversion GO = 0 ADIF = 1
Wake-up Yes From Sleep?
Wait 2 TAD
No
Finish Conversion GO = 0 ADIF = 1
SLEEP Power-down A/D
Wait 2 TAD
Stay in Sleep Power-down A/D
Wait 2 TAD
TABLE 8-2:
Address 0Bh/8Bh 0Ch 8Ch 1Eh 1Fh 9Fh Name
SUMMARY OF A/D REGISTERS
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 GPIE -- -- Bit 2 T0IF -- -- Bit 1 INTF -- -- Bit 0 GPIF -- -- Value on Power-on Reset 0000 000x -0-- ----0-- ---xxxx xxxx r -- CHS1 -- CHS0 -- GO/DONE PCFG2 r PCFG1 ADON PCFG0 0000 0000 ---- -000 --xx xxxx Value on all other Resets(1) 0000 000u -0-- ----0-- ---uuuu uuuu 0000 0000 ---- -000 --uu uuuu
INTCON PIR1 PIE1 ADRES ADCON0 ADCON1
A/D Result Register ADCS1 -- ADCS0 --
05h GPIO -- -- GP5 GP4 GP3 GP2 GP1 GP0 85h TRIS -- -- TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0', r = reserved. Shaded cells are not used for A/D conversion. Note 1: These registers can be addressed from either bank.
DS40181B-page 44
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
9.0 SPECIAL FEATURES OF THE CPU
the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC12CE67X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming The PIC12CE67X has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep
9.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h3FFFh), which can be accessed only during programming.
FIGURE 9-1:
CP1 bit13 CP0
CONFIGURATION WORD
CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0 bit0
Register: Address
CONFIG 2007h
bit 13-8, CP1:CP0: Code Protection bit pairs (1) 6-5: 11 = Code protection off 10 = Locations 400h through 7FEh code protected (do not use for PIC12CE673) 01 = Locations 200h through 7FEh code protected 00 = All memory is code protected bit 7: MCLRE: Master Clear Reset Enable bit 1 = Master Clear Enabled 0 = Master Clear Disabled PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC2:FOSC0: Oscillator Selection bits 111 = EXTRC, Clockout on OSC2 110 = EXTRC, OSC2 is I/O 101 = INTRC, Clockout on OSC2 100 = INTRC, OSC2 is I/O 011 = Invalid Selection 010 = HS Oscillator 001 = XT Oscillator 000 = LP Oscillator
bit 4:
bit 3:
bit 2-0:
Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 45
PIC12CE67X
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC12CE67X
Cap. Range C1 Cap. Range C2
The PIC12CE67X can be operated in seven different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these seven modes: * * * * * LP: HS: XT: INTRC*: EXTRC*: Low Power Crystal High Speed Crystal Resonator Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor
Osc Type XT
Resonator Freq
*Can be configured to support CLKOUT 9.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS
455 kHz 22-100 pF 22-100 pF 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF HS 4.0 MHz 15-68 pF 15-68 pF 8.0 MHz 10-68 pF 10-68 pF 10.0 MHz 10-22 pF 10-22 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 9-2:
In XT, HS or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 9-2). The PIC12CE67X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, HS or LP modes, the device can have an external clock source drive the GP5/OSC1/CLKIN pin (Figure 9-3).
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC12CE67X
Cap.Range C1 Cap. Range C2
Osc Type LP
Resonator Freq
FIGURE 9-2:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT, HS OR LP OSC CONFIGURATION)
OSC1
C1(1)
PIC12CE67X
SLEEP
XTAL RS(2) C2(1) OSC2
RF(3)
To internal logic
Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (approx. value = 10 M).
32 kHz(1) 15 pF 15 pF 100 kHz 15-30 pF 30-47 pF 200 kHz 15-30 pF 15-82 pF 200-300 pF 15-30 pF XT 100 kHz 100-200 pF 15-30 pF 200 kHz 15-100 pF 15-30 pF 455 kHz 15-30 pF 15-30 pF 1 MHz 15-30 pF 15-30 pF 2 MHz 15-47 pF 15-47 pF 4 MHz HS 4 MHz 15-30 pF 15-30 pF 8 MHz 15-30 pF 15-30 pF 10 MHz 15-30 pF 15-30 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
FIGURE 9-3:
EXTERNAL CLOCK INPUT OPERATION (XT, HS OR LP OSC CONFIGURATION)
OSC1 PIC12CE67X
Clock from ext. system Open
OSC2
DS40181B-page 46
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 9.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC12CE67X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 9-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.
FIGURE 9-4:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC12CE67X CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 9-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 9-6:
VDD Rext
EXTERNAL RC OSCILLATOR MODE
FIGURE 9-5:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 74AS04 To Other Devices PIC12CE67X CLKIN
OSC1 N
Internal clock
Cext VSS FOSC/4
330 74AS04 0.1 F XTAL
PIC12CE67X OSC2/CLKOUT
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 47
PIC12CE67X
9.2.5 INTERNAL 4 MHz RC OSCILLATOR
9.3
Reset
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C, see "Electrical Specifications" section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of the program memory which contains the calibration value for the internal RC oscillator. This value is programmed as a RETLW XX instruction where XX is the calibration value. In order to retrieve the calibration value, issue a CALL YY instruction where YY is the last location in program memory (03FFh for the PIC12CE673, 07FFh for the PIC12CE674). Control will be returned to the user's program with the calibration value loaded into the W register. The program should then perform a MOVWF OSCCAL instruction to load the value into the internal RC oscillator trim register. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. Only bits <7:2> of OSCCAL are implemented, and bits <1:0> should be written as 0 for compatibility with future devices. The oscillator calibration location is not code protected. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part. CLKOUT
The PIC12CE67X differentiates between various kinds of reset: * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation)
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), MCLR Reset, WDT Reset, and MCLR Reset during SLEEP. They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the reset. See Table 9-5 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 9-7. The PIC12CE67X has a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
9.2.6
The PIC12CE67X can be configured to provide a clock out signal (CLKOUT) on pin 3 when the configuration word address (2007h) is programmed with FOSC2, FOSC1, FOSC0 equal to 101 for INTRC or 111 for EXTRC. The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic.
DS40181B-page 48
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak Pull-up
GP3/MCLR/VPP Pin
MCLRE INTERNAL MCLR
WDT SLEEP Module WDT Time-out VDD rise detect VDD S OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset Power-on Reset
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 49
PIC12CE67X
9.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
POWER-ON RESET (POR) 9.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 9.4.4 TIME-OUT SEQUENCE
9.4.1
The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." 9.4.2 POWER-UP TIMER (PWRT)
On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 9-8, Figure 9-9, and Figure 9-10 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 9-9). This is useful for testing purposes or to synchronize more than one PIC12CE67X device operating in parallel. Table 9-5 shows the reset conditions for all the registers. 9.4.5 POWER CONTROL (PCON)/STATUS REGISTER
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
The power control/status register, PCON (address 8Eh) has one bit. See Figure 4-8 for register. Bit1 is POR (Power-on Reset). It is cleared on a Poweron Reset and is unaffected otherwise. The user set this bit following a Power-on Reset. On subsequent resets if POR is `0', it will indicate that a Power-on Reset must have occurred.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 PWRTE = 1 72 ms + 1024TOSC 1024TOSC 72 ms -- Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP INTRC, EXTRC
TABLE 9-4:
POR 0 0 0 1 1 1 1 TO 1 0 x 0 0 u 1
STATUS/PCON BITS AND THEIR SIGNIFICANCE
PD 1 x 0 u 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset during normal operation WDT Wake-up from SLEEP Interrupt wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu uuu1 0uuu
PCON Register ---- --0---- --u---- --u---- --u---- --u---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 9-6:
Register W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 ADCON0 OPTION TRIS PIE1 PCON OSCCAL ADCON1
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx 11xx xxxx ---0 0000 0000 000x -0-- ---0000 0000 1111 1111 --11 1111 -0-- ------- --01000 00----- -000 MCLR Resets WDT Reset uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu 11uu uuuu ---0 0000 0000 000u -0-- ---0000 0000 1111 1111 --11 1111 -0-- ------- --uuuuu uu----- -000 Wake-up via WDT or Interrupt uuuu uuuu 0000 0000 uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu 11uu uuuu ---u uuuu uuuu uqqq(1) -q-- ----(4) uuuu uquu(5) uuuu uuuu --uu uuuu -u-- ------- --uuuuu uu----- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 9-5 for reset value for specific condition. 4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u. 5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 51
PIC12CE67X
FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS40181B-page 52
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D R R1 MCLR C PIC12CE67X
FIGURE 9-12: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD 33k 10k 4.3k VDD
MCLR PIC12CE67X
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal brown-out detection should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
FIGURE 9-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD R1 Q1
VDD
MCLR R2 4.3k PIC12CE67X
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 = 0.7V VDD * R1 + R2 2: Internal brown-out detection should be disabled, if available, when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 53
PIC12CE67X
9.5 Interrupts
There are four sources of interrupt: Interrupt Sources TMR0 overflow interrupt External interrupt GP2/INT pin GPIO Port change interrupts (pins GP0, GP1, GP3) A/D Interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The GP2/INT, GPIO port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flag ADIF, is contained in the special function register PIR1. The corresponding interrupt enable bit is contained in special function register PIE1, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-15). The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset.
FIGURE 9-14: INTERRUPT LOGIC
T0IF T0IE INTF INTE GPIF GPIE ADIF ADIE PEIE Interrupt to CPU Wakeup (If in SLEEP mode)
GIE
DS40181B-page 54
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-15: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 1 Interrupt Latency 2
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTRC and EXTRC oscillator modes. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 55
PIC12CE67X
9.5.1 TMR0 INTERRUPT
9.6
Context Saving During Interrupts
An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 7.0) 9.5.2 INT INTERRUPT
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 9-1 store and restore the STATUS and W registers. The register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W register.
External interrupt on GP2/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.8 for details on SLEEP mode. 9.5.3 GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit GPIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit GPIE (INTCON<3>). (Section 5.1)
EXAMPLE 9-1:
MOVWF SWAPF BCF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP STATUS,W STATUS,RP0 STATUS_TEMP ;Copy W to TEMP ;Swap status to ;Change to bank ;Save status to register, could be bank one or zero be saved into W zero, regardless of current bank bank zero STATUS_TEMP register
STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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9.7 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 9.1). 9.7.1 WDT PERIOD The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out early and generating a premature device RESET condition. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 9.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler) it may take several seconds before a WDT time-out occurs. Note: When the prescaler is assigned to the WDT, always execute a CLRWDT instruction before changing the prescale value, otherwise a WDT reset may occur.
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 7-5) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 7-5) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT Time-out
FIGURE 9-17: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h Name Config. bits(1) OPTION Bit 7 MCLRE GPPU Bit 6 CP1 INTEDG Bit 5 CP0 T0CS Bit 4 PWRTE T0SE Bit 3 WDTE PSA Bit 2 FOSC2 PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
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9.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input if enabled should also be at VDD or VSS for lowest current consumption. The contribution from onchip pull-ups on GPIO should be considered. The MCLR pin if enabled must be at a logic high level (VIHMC). 9.8.1 WAKE-UP FROM SLEEP Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 9.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). GP2/INT interrupt, interrupt GPIO port change, or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupt can wake the device from SLEEP: 1. A/D conversion (when A/D clock source is RC).
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FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) GPIO pin GPIF flag (INTCON<0>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
9.9
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
9.10
ID Locations
After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12CE67X Programming Specifications.
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used.
FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC12CE67X VDD VSS MCLR/VPP GP1 GP0
External Connector Signals +5V 0V VPP CLK Data I/O
9.11
In-Circuit Serial Programming
PIC12CE67X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 (clock) becomes the programming clock and GP0 (data) becomes the programming data. Both GP0 and GP1 are Schmitt Trigger inputs in this mode.
VDD To Normal Connections
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NOTES:
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10.0 INSTRUCTION SET SUMMARY
Each PIC12CE67X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC12CE67X instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 101 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 10-2 lists the instructions recognized by the MPASM assembler. Figure 10-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PIC12CE67X products, do not use the OPTION and TRIS instructions.
TABLE 10-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name TOS Top of Stack PC Program Counter
PCLATH Program Counter High Latch
FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 87 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 0 0
GIE WDT TO PD dest []
() <> italics
Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
0 k (literal)
k = 11-bit immediate value
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10.1 Special Function Registers as Source/Destination
10.1.3 PCL AS SOURCE OR DESTINATION Read, write or read-modify-write on PCL may have the following results: Read PC: Write PCL: Read-Modify-Write: PCL dest PCLATH PCH; 8-bit destination value PCL PCL ALU operand PCLATH PCH; 8-bit result PCL
The PIC12CE67X's orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations the user should be aware of: 10.1.1 STATUS AS DESTINATION
If an instruction writes to STATUS, the Z, C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written. For example, executing CLRF STATUS will clear register STATUS, and then set the Z bit leaving 0000 0100b in the register. 10.1.2 TRIS AS DESTINATION
Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, dest = destination, WREG or f. 10.1.4 BIT MANIPULATION
Bit 3 of the TRIS register always reads as a '1' since GP3 is an input only pin. This fact can affect some readmodify-write operations on the TRIS register.
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and writing the result back (read-modify-write). The user should keep this in mind when operating on special function registers, such as ports.
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TABLE 10-2:
Mnemonic, Operands
INSTRUCTION SET SUMMARY
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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10.2
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
And Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
Words: Cycles: Example
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Words: Cycles: Example
1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
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BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction.
Before Instruction After Instruction
FLAG_REG = 0x47
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
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BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2 cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSS GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0000 0011 W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
Words: Cycles: Example
1 2
HERE CALL THERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE TOS = Address HERE+1
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CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescaler= TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
skip if result = 0
Words: Cycles: Example
1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
1 1(2)
HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP
Before Instruction After Instruction
REG1 W
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
HERE INCFSZ GOTO CONTINUE * * * CNT, LOOP 1
After Instruction
PC =
Example
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example
1 1
IORLW W 0x35 = = = 0x9A 0xBF 1
Words: Cycles: Example
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction After Instruction
W Z
Before Instruction
After Instruction
CNT Z
DS40181B-page 68
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
Words: Cycles: Example
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1
Words: Cycles: Example
1 1
MOVF FSR, 0 W = value in FSR register Z =1
Before Instruction
After Instruction
RESULT = W = Z =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
f
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 69
PIC12CE67X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction.
NOP
RETFIE
No operation.
Words: Cycles: Example
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC12C67X products, do not use this instruction.
Words: Cycles: Example
1 2
CALL TABLE * * * TABLE ADDWF RETLW RETLW * * * RETLW ;W contains table ;offset value ;W now has table value ;W = offset ;Begin table ;
PC k1 k2
kn
; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
DS40181B-page 70
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
RETURN
Words: Cycles: Example
1 2
RETURN
After Interrupt
PC = TOS
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.
RLF
f,d
SLEEP
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Words: Cycles: Example:
1 1 SLEEP
Before Instruction
After Instruction
REG1 W C
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 71
PIC12CE67X
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff SUBWF f,d
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example 1:
1 1 SUBLW 0x02
W C = = 1 ?
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Example 1:
1 1 SUBWF
REG1 W C
Before Instruction
REG1,1
= = = 3 2 ?
Before Instruction
After Instruction
W C = = 1 1; result is positive
Example 2:
Before Instruction
W C = = 2 ?
After Instruction
REG1 W C = = = 1 2 1; result is positive
After Instruction
W C = = 0 1; result is zero
Example 2:
Before Instruction
REG1 W C = = = 2 2 ?
Example 3:
Before Instruction
W C = = 3 ?
After Instruction
REG1 W C = = = 0 2 1; result is zero
After Instruction
W= C = tive 0xFF 0; result is nega-
Example 3:
Before Instruction
REG1 W C = = = 1 2 ?
After Instruction
REG1 W C = = = 0xFF 2 0; result is negative
DS40181B-page 72
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Cycles: Example:
1 1 XORLW 0xAF
W = 0xB5
Words: Cycles: Example
1 1
SWAPF REG, 0
Before Instruction After Instruction
W = = 0xA5 0x5A = 0x1A
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Status Affected: None
00
0000
0110
0fff
Status Affected: Encoding: Description:
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC12C67X products, do not use this instruction.
Words: Cycles: Example
1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 73
PIC12CE67X
NOTES:
DS40181B-page 74
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
11.0
11.1
DEVELOPMENT SUPPORT
Development Tools
11.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * MPLABTM-ICE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP) * KEELOQ(R) Evaluation Kits and Programmer
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through PentiumTM based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.
11.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
11.2
MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU.
11.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 75
PIC12CE67X
11.6 SIMICE Entry-Level Hardware Simulator 11.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip's simulator MPLABTM-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology's MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip's PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicroTM 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development.
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
11.7
PICDEM-1 Low-Cost PICmicro Demonstration Board
11.9
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS40181B-page 76
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
11.10 MPLAB Integrated Development Environment Software 11.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
11.13
MPLAB-C17 Compiler
The MPLAB-C17 Code Development System is a complete ANSI `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
11.14
Fuzzy Logic Development System (fuzzyTECH-MP)
11.11
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip's Universal Emulator System. MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
11.15
SEEVAL(R) Evaluation and Programming System
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 77
PIC12CE67X
11.16 KEELOQ(R) Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS40181B-page 78
Preliminary
(c) 1998 Microchip Technology Inc.
Software Tools
Programmers
Demo Boards
(c) 1998 Microchip Technology Inc.
TABLE 11-1:
PIC12C5XX Emulator Products
PIC14000
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
MPLABTM-ICE
u
u
u
u
u
u
u
u
u
u
DEVELOPMENT TOOLS FROM MICROCHIP
ICEPICTM Low-Cost In-Circuit Emulator MPLABTM Integrated Development Environment MPLABTM C17* Compiler u u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
fuzzyTECH(R)-MP
Explorer/Edition Fuzzy Logic Dev. Tool Total EnduranceTM Software Model PICSTART(R)Plus Low-Cost Universal Dev. Kit PRO MATE(R) II Universal Programmer KEELOQ(R) Programmer SEEVAL(R) Designers Kit SIMICE PICDEM-14A PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ(R) Evaluation Kit KEELOQ Transponder Kit u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u
Preliminary
DS40181B-page 79
u
u
u
u
u
u
u
u
u
u
u
u
u u
PIC12CE67X
PIC12CE67X
NOTES:
DS40181B-page 80
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
12.0 ELECTRICAL CHARACTERISTICS FOR PIC12CE67X
Absolute Maximum Ratings Ambient temperature under bias............................................................................................................. .-40 to +125C Storage temperature ............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V Total power dissipation (Note 1)...........................................................................................................................700 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................125 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by GPIO pins combined ...................................................................................................100 mA Maximum current sourced by GPIO pins combined..............................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 81
DS40181B-page 82 OSC PIC12CE673-04 PIC12CE674-04 PIC12CE673-10 PIC12CE674-10 PIC12LCE673-04 PIC12LCE674-04 PIC12CE673/JW PIC12CE674/JW INTRC VDD: 3.0V to 5.5V VDD: 3.0V to 5.5V VDD: 2.5V to 5.5V VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 2.5V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 0.9 A typ. at 2.5V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 3.0V to 5.5V VDD: 3.0V to 5.5V VDD: 2.5V to 5.5V VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 2.5V IDD: 5 mA max. at 5.5V EXTRC IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 0.9 A typ. at 2.5V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 3.0V to 5.5V VDD: 3.0V to 5.5V VDD: 2.5V to 5.5V VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 2.5V IDD: 5 mA max. at 5.5V XT IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 0.9 A typ. at 2.5V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V HS N/A IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 10 MHz max. VDD: 3.0V to 5.5V VDD: 2.5V to 5.5V VDD: 3.0V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IDD: 48 A max. at 32 kHz, 2.5V IDD: 48 A max. at 32 kHz, 2.5V N/A LP IPD: 0.9 A typ. at 4.0V IPD: 5.0 A max. at 2.5V IPD: 5.0 A max. at 2.5V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
TABLE 12-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC12CE67X
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
12.1 DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended(5)) PIC12CE673-10 (Commercial, Industrial, Extended(5)) PIC12CE674-04 (Commercial, Industrial, Extended(5)) PIC12CE674-10 (Commercial, Industrial, Extended(5))
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym Min Typ Max Units VDD 3.0 4.5 RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2) No read/write to EEPROM peripheral VDR VPO
R
DC CHARACTERISTICS
Parm No. D001 D001A D002 D003
Characteristic Supply Voltage
Conditions XT, INTRC, EXTRC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
1.5 -
5.5 5.5 VSS
V V V V
VSS
D004 D010
SVD
D
0.05 -
2.7
3.3
V/ms See section on Power-on Reset for details mA XT, EXTRC osc configuration (PIC12CE67X-04) FOSC = 4 MHz, VDD = 5.5V (Note 4) INTRC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 6) HS osc configuration (PIC12CE67X-10) FOSC = 10 MHz, VDD = 5.5V VDD = 5.5V SCL = 400 kHz
IDD
D010A D013 D028 IEE -
2.7 TBD 0.1
3.3 15 0.2
mA mA
Power-down Current (Note 3) IPD D020 D021 D021A D021B
-
5.5 1.5 1.5 1.5
32 16 14 TBD
A A A A
VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, 0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C
* Note 1: 2:
3: 4: 5: 6:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For EXTRC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Extended operating range is Advance Information for this device. INTRC calibration value is for 4 MHz nominal at 5V, 35C.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 83
PIC12CE67X
12.2 DC Characteristics: PIC12LCE673-04 (Commercial, Industrial) PIC12LCE674-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Sym VDD VDR VPOR Min 2.5 Typ Max Units TBD VSS 5.5 V V V Conditions XT, INTRC, EXTRC and LP osc configuration (DC - 4 MHz) Device in SLEEP mode See section on Power-on Reset for details
DC CHARACTERISTICS Param No. D001 D002* D003 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2)
D004*
SVDD
TBD
-
-
V/ms See section on Power-on Reset for details
D010 D010B
IDD
-
TBD TBD TBD TBD
mA mA A A A A
D010A D020 D021 D021A * Note 1: 2: Power-down Current (Note 3) IPD TBD TBD TBD TBD TBD
XT, EXTRC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) INTRC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 5) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For EXTRC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. INTRC calibration value is for 4 MHz nominal at 5V, 25C.
DS40181B-page 84
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
12.3 DC Characteristics: PIC12CE673-04 PIC12CE673-10 PIC12CE674-04 PIC12CE674-10 (Commercial, Industrial, Extended(4)) (Commercial, Industrial, Extended(4)) (Commercial, Industrial, Extended(4)) (Commercial, Industrial, Extended(4))
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH 2.0 0.8VDD 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 0.5V 0.2VDD 0.2VDD 0.3VDD V V V V Note1
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT OSC1 (XT, HS and LP) OSC1 (in EXTRC mode) GPIO weak pull-up current IPUR Input Leakage Current (Notes 2, 3) I/O ports IIL MCLR, GP2/T0CKI OSC1 Output Low Voltage I/O ports/CLKOUT
VDD VDD VDD VDD VDD VDD 400 +1 +5(5) +5
V V V V V V A
4.5 VDD 5.5V For VDD > 5.5V or VDD < 4.5V For entire VDD range Note1 VDD = 5V, VPIN = VSS
A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V
D080 D080A D083 D083A Note 1: 2: 3: 4: 5:
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C OSC2 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
VOL
-
-
0.6
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 85
PIC12CE67X
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 VDD - 0.7 OSC2 VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins OSC2 pin V V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C
DC CHARACTERISTICS
Param No. D090 D090A D092 D092A
Characteristic Output High Voltage I/O ports/CLKOUT (Note 3)
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 Note 1: 2: 3: 4: 5:
All I/O pins and OSC2 CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
DS40181B-page 86
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
12.4 DC Characteristics: PIC12LCE671-04 (Commercial, Industrial) PIC12LCE672-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD V V V V Note1
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT OSC1 (XT, HS and LP) OSC1 (in EXTRC mode) GPIO weak pull-up current IPUR Input Leakage Current (Notes 2, 3) I/O ports IIL MCLR, GP3 OSC1 Output Low Voltage I/O ports/CLKOUT
VDD VDD VDD VDD VDD VDD TBD TBD TBD TBD
V V V V V V A
4.5 VDD 5.5V For VDD > 5.5V or VDD < 4.5V For entire VDD range Note1 VDD = 5V, VPIN = VSS
A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V V V V IOL = TBD, VDD = 4.5V, -40C to +85C IOL = TBD, VDD = 4.5V, -40C to +125C IOL = TBD, VDD = 4.5V, -40C to +85C IOL = TBD, VDD = 4.5V, -40C to +125C
D080 D080A D083 D083A
VOL
-
TBD TBD TBD TBD
0.6 0.6 0.6 0.6
OSC2
-
D090 D090A D092 D092A Note 1: 2: 3: 4:
IOH = TBD, VDD = 4.5V, -40C to +85C VDD - 0.7 V IOH = TBD, VDD = 4.5V, -40C to +125C OSC2 VDD - 0.7 V IOH = TBD, VDD = 4.5V, -40C to +85C VDD - 0.7 V IOH = TBD, VDD = 4.5V, -40C to +125C Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device.
Output High Voltage I/O ports/CLKOUT (Note 3)
VOH
VDD - 0.7
-
-
V
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 87
PIC12CE67X
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ Max Units Conditions
Param No.
Characteristic Capacitive Loading Specs on Output Pins OSC2 pin
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 Note 1: 2: 3: 4:
All I/O pins and OSC2 CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device.
DS40181B-page 88
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
12.5 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
FIGURE 12-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 89
PIC12CE67X
12.6 Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 12-2:
Parameter No. Sym Fosc
CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min Typ Max Units Conditions
DC -- 4 MHz XT and EXTRC osc mode DC -- 4 MHz HS osc mode (PIC12CE67X-04) DC -- 10 MHz HS osc mode (PIC12CE67X-10) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz EXTRC osc mode (Note 1) .455 -- 4 MHz XT osc mode 4 -- 4 MHz HS osc mode (PIC12CE67X-04) 4 -- 10 MHz HS osc mode (PIC12CE67X-10) 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT and EXTRC osc mode (Note 1) 250 -- -- ns HS osc mode (PIC12CE67X-04) 100 -- -- ns HS osc mode (PIC12CE67X-10) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns EXTRC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (PIC12CE67X-04) 100 -- 250 ns HS osc mode (PIC12CE67X-10) 5 -- -- s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 400 -- DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High 50 -- -- ns XT oscillator TosH or Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC12CE67X.
DS40181B-page 90
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Characteristic
Internal Calibrated RC Frequency Internal Calibrated RC Frequency * These parameters are characterized but not tested.
AC Characteristics
Parameter No.
Sym
Min* Typ(1)
TBD TBD 4.00 4.00
Max* Units
TBD TBD
Conditions
MHz VDD = 5.0V MHz VDD = 2.5V
Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 91
PIC12CE67X
FIGURE 12-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 12-1 for load conditions. 15 new value 19 18 12 16 11 Q1 Q2 Q3
TABLE 12-4:
Parameter Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* *
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time GPIO change INT high or low time PIC12CE67X PIC12CE67X Min -- -- -- -- -- 0.25TCY + 25 0 -- TBD TBD -- -- 20 20 Typ 15 15 5 5 -- -- -- -- -- -- 10 10 -- -- Max 30 30 15 15 0.5TCY + 20 -- -- 80 - 100 -- -- 25 25 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
DS40181B-page 92
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET 32 30
Watchdog Timer RESET
34 31 34
36
I/O Pins
TABLE 12-5:
Parameter No. 30 31* 32 33* 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Min 2 7 -- 28 -- Typ -- 18 1024TOSC 72 -- Max -- 33 -- 132 2.1 Units s ms -- ms s Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 93
PIC12CE67X
FIGURE 12-5: TIMER0 CLOCK TIMINGS
GP2/T0CKI
40 42
41
TMR0
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-6:
Param No. 40 Sym Tt0H
TIMER0 CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler Min 0.5TCY + 20* 10* 0.5TCY + 20* 10* Greater of: 20s or TCY + 40* N 2Tosc Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns N = prescale value (1, 2, 4,..., 256)
41
Tt0L
T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P
T0CKI Period
48 *
Tcke2tmrI Delay from external clock edge to timer increment
--
7Tosc
--
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 12-7:
VDD (Volts) 2.5
GPIO PULL-UP RESISTOR RANGES
Temperature (C) -40 25 85 125 -40 25 85 125 -40 25 85 125 -40 25 85 125 Min GP0/GP1 38K 42K 42K 50K 15K 18K 19K 22K GP3 285K 343K 368K 431K 247K 288K 306K 351K 42K 48K 49K 55K 17K 20K 22K 24K 346K 414K 457K 504K 292K 341K 371K 407K 63K 63K 63K 63K 20K 23K 25K 28K 417K 532K 532K 593K 360K 437K 448K 500K Typ Max Units
5.5
2.5
5.5
*
These parameters are characterized but not tested.
DS40181B-page 94
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
TABLE 12-8: A/D CONVERTER CHARACTERISTICS: PIC12CE673-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3)) PIC12CE673-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3)) PIC12CE674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED(3)) PIC12CE674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED(3))
Characteristic Resolution Integral error Differential error Full scale error Offset error Monotonicity Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) VREF input current (Note 2) Min -- -- -- -- -- -- 3.0V VSS - 0.3 -- Typ -- -- -- -- -- Typ -- -- -- Max 8-bits less than 1 LSb less than 1 LSb less than 1 LSb less than 1 LSb -- VDD + 0.3 VREF + 0.3 10.0 Units -- -- -- -- -- -- V V k Conditions VREF = VDD = 5.12V, VSS AIN VREF (Notes 4,5) VREF = VDD = 5.12V, VSS AIN VREF (Notes 4,5) VREF = VDD = 5.12V, VSS AIN VREF (Notes 4,5) VREF = VDD = 5.12V, VSS AIN VREF (Notes 4,5) VREF = VDD = 5.12V, VSS AIN VREF (Notes 4,5) VSS AIN VREF
Parameter No.
Sym NR NINT NDIF NFS NOFF -- VREF VAIN ZAIN
IAD IREF * Note 1: 2: 3: 4:
-- --
180 --
-- 1 10
A mA A
Average current consumption when A/D is on. (Note 1) During sampling All other times
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from GP1 pin or VDD pin, whichever is selected as reference input. Extended operating range is Advance Information for this device. These specifications apply if VREF = 3.0V and if VDD 3.0V. VIN must be between VSS and VREF
5: When using external VREF, VDD must be greater than 3V for +1 LSB accuracy. If VDD is less than 3V, you must use internal VREF for +1 LSB.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 95
PIC12CE67X
TABLE 12-9: A/D CONVERTER CHARACTERISTICS: PIC12LCE673-04 (COMMERCIAL, INDUSTRIAL) PIC12LCE674-04 (COMMERCIAL, INDUSTRIAL)
Sym NR NINT NDIF NFS NOFF -- VREF VAIN ZAIN Characteristic Resolution Integral error Differential error Full scale error Offset error Monotonicity Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) VREF input current (Note 3) Min -- -- -- -- -- -- TBD VSS - 0.3 -- Typ -- -- -- -- -- Typ -- -- -- Max 8-bits less than 1 LSb less than 1 LSb less than 1 LSb less than 1 LSb -- VDD + 0.3 VREF + 0.3 10.0 Units -- -- -- -- -- -- V V k Conditions VREF = VDD = 3.0V (Notes 1,4) VREF = VDD = 3.0V (Notes 1,4) VREF = VDD = 3.0V (Notes 1,4) VREF = VDD = 3.0V (Notes 1,4) VREF = VDD = 3.0V (Notes 1,4) VSS AIN VREF
Parameter No.
IAD IREF *
-- --
TBD --
-- TBD TBD
A mA A
Average current consumption when A/D is on. (Note 2) During sampling All other times
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications apply if VREF = 3.0V and if VDD 3.0V. VIN must be between VSS and VREF 2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 3: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
4: When using external VREF, VDD must be greater than 3V for +1 LSB accuracy. If VDD is less than 3V, you must use internal VREF for +1 LSB.
DS40181B-page 96
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 12-6: A/D CONVERSION TIMING
BSF ADCON0, GO (TOSC/2) (1) Q4 130 A/D CLK 132 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-10: A/D CONVERSION REQUIREMENTS
Parameter No. 130 130 Sym TAD TAD Characteristic A/D clock period A/D Internal RC Oscillator source 3.0 2.0 131 TCNV Conversion time (not including S/H time). Note 1 Acquisition time -- 6.0 4.0 9.5TAD 9.0 6.0 -- s s -- Min 1.6 2.0 Typ Max -- -- Units s s Conditions VREF 3.0V VREF full range ADCS1:ADCS0 = 11 (RC oscillator source) PIC12LCE67X, VDD = 3.0V PIC12CE67X
132 *
TACQ
Note 2
20
--
s
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 97
PIC12CE67X
NOTES:
DS40181B-page 98
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
13.0 DC AND AC CHARACTERISTICS - PIC12CE67X
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation.
FIGURE 13-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
TO BE DETERMINED
FIGURE 13-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 3.0V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
TO BE DETERMINED
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 99
PIC12CE67X
TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25C
Frequency VDD = 2.5V TBD A* TBD A TBD A TBD A VDD = 5.5V 620 A* 1.1 mA 775 A 37 A Oscillator
External RC 4 MHz Internal RC 4 MHz XT 4 MHz LP 32 KHz *Does not include current through external R&C.
FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs. VDD
50 45 40 35 WDT period (s) 30
Max +125C
25 20
Max +85C
Typ +25C
15 10
MIn -40C
5 2 3 4 5 VDD (Volts) 6 7
DS40181B-page 100
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V
0
FIGURE 13-6: IOL vs. VOL, VDD = 2.5 V
25
-1
20
-2
Max -40C
IOH (mA)
-3
15 IOL (mA)
Typ +25C
-4
10
-5
Max -40C Typ +25C
Min +85C
-6
M
5C in +12
5
Min +125C
Min +
85C
-7 500m
1.0
1.5
2.0
2.5
0 0 250.0m 500.0m 1.0 VOL (Volts)
VOH (Volts)
FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V FIGURE 13-7: IOL vs. VOL, VDD = 3.5 V
0 -3
40
Max -40C
-5
-8
30
IOH (mA)
-10
Typ +25C
IOL (mA)
20
Min +85C
-13
Ma x C -40
p Ty
+2
5
C
-15
M in 2 +1
5
C
Min +125C
-18 -20 .50 1.5
M
in
+8
C 5
10
0
2.0 2.5 3.0
0
.50 VOL (Volts)
.75
1.0
VOH (Volts)
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 101
PIC12CE67X
FIGURE 13-8: IOH vs. VOH, VDD = 5.5 V
0
FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V
50
-5
Max -40C
40
-10
IOH (mA)
30
-15
C
Typ +25C
IOL (mA)
M
M in
+8
C
5 C
-20
in
+1
25
20
Min +85C
Ty p
+2
0
-25
C
5
Min +125C
-30 3.5 4.0 4.5 5.0 5.5
M
ax
-4
10
0 .25 .50 .75 1.0 VOL (Volts)
VOH (Volts)
DS40181B-page 102
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
14.0
14.1
PACKAGING INFORMATION
Package Marking Information 8-Lead PDIP (300 mil) MMMMMMMM XXXXXCDE AABB
Example 12CE674 04/PSAZ 9725
8-Lead Windowed Ceramic Side Brazed (300 mil) MM
Example JW
MMMMMM
CE674
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 103
PIC12CE67X
Package Type: K04-018 8-Lead Plastic Dual In-line (P) - 300 mil
E
D 2 1 E1
n
A A1
R
c
L A2
eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
B1 p B INCHES* NOM 0.300 8 0.100 0.018 0.014 0.060 0.055 0.005 0.000 0.012 0.006 0.150 0.140 0.080 0.060 0.020 0.005 0.130 0.120 0.370 0.355 0.250 0.245 0.280 0.267 0.310 0.342 5 10 5 10 MILLIMETERS NOM MAX 7.62 8 2.54 0.56 0.36 0.46 1.65 1.40 1.52 0.25 0.00 0.13 0.38 0.20 0.29 4.06 3.56 3.81 2.54 1.52 2.03 0.89 0.13 0.51 3.56 3.05 3.30 9.78 9.02 9.40 6.60 6.22 6.35 7.42 6.78 7.10 7.87 8.67 9.65 5 10 15 5 10 15
MIN n p B B1 R c A A1 A2 L D E E1 eB
MAX
MIN
0.022 0.065 0.010 0.015 0.160 0.100 0.035 0.140 0.385 0.260 0.292 0.380 15 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS40181B-page 104
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) - 300 mil
E
W
T 2 n 1
D
U
A
A1
L A2 c eB B1 p B
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Lead Thickness Top to Seating Plane Top of Body to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Overall Row Spacing Window Diameter Lid Length Lid Width * Controlling Parameter.
MIN n p B B1 c A A1 A2 L D E eB W T U
0.098 0.016 0.050 0.008 0.145 0.103 0.025 0.130 0.510 0.280 0.310 0.161 0.440 0.260
INCHES* NOM 0.300 8 0.100 0.018 0.055 0.010 0.165 0.123 0.035 0.140 0.520 0.290 0.338 0.166 0.450 0.270
MAX
MIN
0.102 0.020 0.060 0.012 0.185 0.143 0.045 0.150 0.530 0.300 0.365 0.171 0.460 0.280
MILLIMETERS NOM MAX 7.62 8 2.54 2.49 2.59 0.41 0.51 0.46 1.27 1.40 1.52 0.20 0.25 0.30 3.68 4.70 4.19 3.12 2.62 3.63 0.89 0.64 1.14 3.56 3.30 3.81 12.95 13.21 13.46 7.11 7.37 7.62 7.87 9.27 8.57 4.09 4.34 4.22 11.18 11.68 11.43 6.60 7.11 6.86
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 105
PIC12CE67X
NOTES:
DS40181B-page 106
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
INDEX A
A/D Accuracy/Error ............................................................ 43 ADCON0 Register....................................................... 37 ADIF bit ....................................................................... 39 Analog Input Model Block Diagram............................. 40 Analog-to-Digital Converter......................................... 37 Configuring Analog Port Pins...................................... 41 Configuring the Interrupt ............................................. 39 Configuring the Module............................................... 39 Connection Considerations......................................... 43 Conversion Clock........................................................ 41 Conversions ................................................................ 42 Converter Characteristics ........................................... 95 Delays ......................................................................... 40 Effects of a Reset........................................................ 43 Equations .................................................................... 40 Flowchart of A/D Operation......................................... 44 GO/DONE bit .............................................................. 39 Internal Sampling Switch (Rss) Impedence ................ 40 Operation During Sleep .............................................. 43 Sampling Requirements.............................................. 40 Sampling Time ............................................................ 40 Source Impedence...................................................... 40 Time Delays ................................................................ 40 Transfer Function........................................................ 43 Absolute Maximum Ratings ................................................ 81 ADDLW Instruction ............................................................. 64 ADDWF Instruction ............................................................. 64 ADIE bit............................................................................... 18 ADIF bit ............................................................................... 19 ADRES Register ..................................................... 13, 37, 39 ALU ....................................................................................... 7 ANDLW Instruction ............................................................. 64 ANDWF Instruction ............................................................. 64 Application Notes AN546 ......................................................................... 37 AN556 ......................................................................... 22 Architecture Harvard ......................................................................... 7 Overview ....................................................................... 7 von Neumann................................................................ 7 Assembler MPASM Assembler..................................................... 77 CALSLW bit ........................................................................ 21 Carry bit .................................................................................7 Clocking Scheme................................................................ 10 CLRF Instruction................................................................. 66 CLRW Instruction ............................................................... 66 CLRWDT Instruction........................................................... 67 Code Examples Changing Prescaler (Timer0 to WDT) ........................ 35 Changing Prescaler (WDT to Timer0) ........................ 35 Indirect Addressing..................................................... 23 Code Protection ............................................................ 45, 59 COMF Instruction ............................................................... 67 Computed GOTO ............................................................... 22 Configuration Bits ............................................................... 45
D
DC bit.................................................................................. 15 DC Characteristics PIC12CE673............................................................... 83 PIC12CE674............................................................... 83 DECF Instruction ................................................................ 67 DECFSZ Instruction............................................................ 67 Development Support ..................................................... 3, 75 Development Tools............................................................. 75 Diagrams - See Block Diagrams Digit Carry bit .........................................................................7 Direct Addressing ............................................................... 23
E
EEPROM Peripheral Operation .......................................... 27 Electrical Characteristics PIC12CE67X .............................................................. 81 Errata .....................................................................................2 External Brown-out Protection Circuit................................. 53 External Power-on Reset Circuit ........................................ 53
F
Family of Devices ..................................................................4 Features ................................................................................1 FSR Register .......................................................... 13, 14, 23 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .................... 77
G
General Description ...............................................................3 GIE bit................................................................................. 54 GOTO Instruction ............................................................... 68 GPIF bit .............................................................................. 56 GPIO............................................................................. 25, 51 GPIO Register .................................................................... 13 GPPU bit............................................................................. 16
B
BCF Instruction ................................................................... 65 Bit Manipulation .................................................................. 62 Block Diagrams Analog Input Model ..................................................... 40 On-Chip Reset Circuit ................................................. 49 Timer0......................................................................... 31 Timer0/WDT Prescaler ............................................... 34 Watchdog Timer.......................................................... 57 BSF Instruction ................................................................... 65 BTFSC Instruction............................................................... 65 BTFSS Instruction............................................................... 66
I
I/O Interfacing ..................................................................... 25 I/O Ports ............................................................................. 25 I/O Programming Considerations ....................................... 26 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 75 ID Locations........................................................................ 45 INCF Instruction.................................................................. 68 INCFSZ Instruction ............................................................. 68 In-Circuit Serial Programming ...................................... 45, 59 INDF Register ............................................................... 14, 23 Indirect Addressing ............................................................. 23 Initialization Conditions for All Registers ............................ 51 Instruction Cycle ................................................................. 10 Instruction Flow/Pipelining .................................................. 10 Instruction Format............................................................... 61 Instruction Set ADDLW....................................................................... 64 ADDWF ...................................................................... 64
C
C bit..................................................................................... 15 CAL0 bit .............................................................................. 21 CAL1 bit .............................................................................. 21 CAL2 bit .............................................................................. 21 CAL3 bit .............................................................................. 21 CALFST bit ......................................................................... 21 CALL Instruction ................................................................. 66
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 107
PIC12CE67X
ANDLW ....................................................................... 64 ANDWF ....................................................................... 64 BCF............................................................................. 65 BSF ............................................................................. 65 BTFSC ........................................................................ 65 BTFSS ........................................................................ 66 CALL ........................................................................... 66 CLRF........................................................................... 66 CLRW ......................................................................... 66 CLRWDT..................................................................... 67 COMF ......................................................................... 67 DECF .......................................................................... 67 DECFSZ...................................................................... 67 GOTO ......................................................................... 68 INCF............................................................................ 68 INCFSZ ....................................................................... 68 IORLW ........................................................................ 68 IORWF ........................................................................ 69 MOVF.......................................................................... 69 MOVLW ...................................................................... 69 MOVWF ...................................................................... 69 NOP ............................................................................ 70 OPTION ...................................................................... 70 RETFIE ....................................................................... 70 RETLW ....................................................................... 70 RETURN ..................................................................... 71 RLF ............................................................................. 71 RRF............................................................................. 71 SLEEP ........................................................................ 71 SUBLW ....................................................................... 72 SUBWF ....................................................................... 72 SWAPF ....................................................................... 73 TRIS............................................................................ 73 XORLW....................................................................... 73 XORWF....................................................................... 73 Section ........................................................................ 61 INTCON Register ................................................................ 17 INTEDG bit.......................................................................... 16 Internal Sampling Switch (Rss) Impedence ........................ 40 Interrupts ............................................................................. 45 A/D .............................................................................. 54 GP2/INT ...................................................................... 54 GPIO Port ................................................................... 54 Section ........................................................................ 54 TMR0 .......................................................................... 56 TMR0 Overflow ........................................................... 54 IORLW Instruction............................................................... 68 IORWF Instruction............................................................... 69 IRP bit ................................................................................. 15 MPLAB Integrated Development Environment Software.... 77
N
NOP Instruction .................................................................. 70
O
Opcode ............................................................................... 61 OPTION Instruction ............................................................ 70 OPTION Register................................................................ 16 Orthogonal ............................................................................ 7 OSC selection..................................................................... 45 OSCCAL Register............................................................... 21 Oscillator EXTRC ....................................................................... 50 HS............................................................................... 50 INTRC......................................................................... 50 LP ............................................................................... 50 XT ............................................................................... 50 Oscillator Configurations..................................................... 46 Oscillator Types EXTRC ....................................................................... 46 HS............................................................................... 46 INTRC......................................................................... 46 LP ............................................................................... 46 XT ............................................................................... 46
P
Package Marking Information ........................................... 103 Packaging Information ...................................................... 103 Paging, Program Memory................................................... 22 PCL..................................................................................... 62 PCL Register .......................................................... 13, 14, 22 PCLATH.............................................................................. 51 PCLATH Register ................................................... 13, 14, 22 PCON Register ............................................................. 20, 50 PD bit ............................................................................ 15, 48 PIC12CE67X DC and AC Characteristics .......................... 99 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 76 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 76 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 76 PICSTART(R) Plus Entry Level Development System ......... 75 PIE1 Register...................................................................... 18 Pinout Description PIC12CE67X ................................................................ 9 PIR1 Register ..................................................................... 19 POP .................................................................................... 22 POR .................................................................................... 50 Oscillator Start-up Timer (OST) ............................ 45, 50 Power Control Register (PCON)................................. 50 Power-on Reset (POR)................................... 45, 50, 51 Power-up Timer (PWRT) ...................................... 45, 50 Power-Up-Timer (PWRT) ........................................... 50 Time-out Sequence .................................................... 50 Time-out Sequence on Power-up ............................... 52 TO............................................................................... 48 Power.................................................................................. 48 Power-down Mode (SLEEP)............................................... 58 Prescaler, Switching Between Timer0 and WDT................ 35 PRO MATE(R) II Universal Programmer .............................. 75 Product Identification System - PIC12CE67X................... 113 Program Branches................................................................ 7 Program Memory Paging ........................................................................ 22 Program Memory Map PIC12CE67X .............................................................. 11 Program Verification ........................................................... 59 PS0 bit ................................................................................ 16 PS1 bit ................................................................................ 16
K
KeeLoq(R) Evaluation and Programming Tools.................... 78
L
Loading of PC ..................................................................... 22
M
MCLR ............................................................................ 48, 51 Memory Data Memory .............................................................. 11 Program Memory ........................................................ 11 Program Memory Map PIC12CE67X....................................................... 11 Register File Map PIC12CE67X....................................................... 12 MOVF Instruction ................................................................ 69 MOVLW Instruction ............................................................. 69 MOVWF Instruction............................................................. 69
DS40181B-page 108
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
PS2 bit ................................................................................ 16 PSA bit ................................................................................ 16 PUSH .................................................................................. 22 Timers Timer0 Block Diagram .................................................... 31 External Clock .................................................... 33 External Clock Timing ........................................ 33 Increment Delay ................................................. 33 Interrupt .............................................................. 31 Interrupt Timing .................................................. 32 Prescaler ............................................................ 34 Prescaler Block Diagram .................................... 34 Section ............................................................... 31 Switching Prescaler Assignment ........................ 35 Synchronization .................................................. 33 T0CKI ................................................................. 33 T0IF .................................................................... 56 Timing................................................................. 31 TMR0 Interrupt ................................................... 56 Timing Diagrams A/D Conversion .......................................................... 97 CLKOUT and I/O ........................................................ 92 External Clock Timing................................................. 90 Time-out Sequence .................................................... 52 Timer0 .................................................................. 31, 94 Timer0 Interrupt Timing .............................................. 32 Timer0 with External Clock......................................... 33 Wake-up from Sleep via Interrupt............................... 59 TO bit .................................................................................. 15 TOSE bit ............................................................................. 16 TRIS Instruction .................................................................. 73 TRIS Register ......................................................... 14, 25, 26 Two's Complement ................................................................7
R
RC Oscillator ....................................................................... 47 Read Modify Write .............................................................. 26 Read-Modify-Write .............................................................. 26 Register File........................................................................ 11 Registers Map PIC12CE67X ...................................................... 12 Reset Conditions......................................................... 51 Reset............................................................................. 45, 48 Reset Conditions for Special Registers .............................. 51 RETFIE Instruction.............................................................. 70 RETLW Instruction.............................................................. 70 RETURN Instruction ........................................................... 71 RLF Instruction.................................................................... 71 RP0 bit .......................................................................... 11, 15 RP1 bit ................................................................................ 15 RRF Instruction ................................................................... 71
S
SEEVAL(R) Evaluation and Programming System............... 77 Services One-Time-Programmable (OTP) .................................. 5 Quick-Turnaround-Production (QTP)............................ 5 Serialized Quick-Turnaround Production (SQTP)......... 5 SFR..................................................................................... 62 SFR As Source/Destination ................................................ 62 SLEEP .......................................................................... 45, 48 SLEEP Instruction............................................................... 71 Software Simulator (MPLAB-SIM) ...................................... 77 Special Features of the CPU .............................................. 45 Special Function Register PIC12CE67X............................................................... 13 Special Function Registers ................................................. 62 Special Function Registers, Section ................................... 12 Stack ................................................................................... 22 Overflows .................................................................... 22 Underflow.................................................................... 22 STATUS Register ............................................................... 15 SUBLW Instruction.............................................................. 72 SUBWF Instruction ............................................................. 72 SWAPF Instruction.............................................................. 73
U
UV Erasable Devices.............................................................5
W
W Register ALU................................................................................7 Wake-up from SLEEP ........................................................ 58 Watchdog Timer (WDT).................................... 45, 48, 51, 57 WDT ................................................................................... 51 Block Diagram ............................................................ 57 Period ......................................................................... 57 Programming Considerations ..................................... 57 Timeout....................................................................... 51 WWW, On-Line Support ........................................................2
T
T0CS bit .............................................................................. 16 TAD...................................................................................... 41 Timer0 RTCC .......................................................................... 51
X
XORLW Instruction ............................................................. 73 XORWF Instruction............................................................. 73
Z
Z bit..................................................................................... 15 Zero bit ..................................................................................7
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 109
PIC12CE67X
DS40181B-page 110
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
DS40181B-page10-111
PIC12CE67X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC12CE67X Questions: 1. What are the best features of this document? Y N Literature Number: DS40181B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40181B-page10-112
(c) 1998 Microchip Technology Inc.
PIC12CE67X
PIC12CE67X PRODUCT IDENTIFICATION SYSTEM
PART NO. -XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Special Requirements P JW I E 04 10 = = = = = = = Examples
a) PIC12CE673-04/P Commercial Temp., PDIP Package, 4 MHz, normal VDD limits PIC12CE673-04I/P Industrial Temp., PDIP package, 4 MHz, normal VDD limits PIC12CE673-10I/P Industrial Temp., PDIP package, 10 MHz, normal VDD limits
300 mil PDIP 300 mil Windowed Ceramic Side Brazed 0C to +70C b) -40C to +85C -40C to +125C 4 MHz/200 kHz 10 MHz
c)
Device
PIC12CE673 PIC12CE674 PIC12LCE673 PIC12LCE674
Please contact your local sales office for exact ordering procedures.
SALES AND SUPPORT
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 113
PIC12CE67X
NOTES:
DS40181B-page 114
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE67X
NOTES:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 115
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dallas
Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Detroit
Microchip Technology Inc. 42705 Grand River, Suite 201 Novi, MI 48375-1727 Tel: 248-374-1888 Fax: 248-374-2874
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 7/7/98
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 8/28/98, Microchip Technology Incorporated, USA. Friday, August 28, 1998
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40181B-page 116
(c) 1998 Microchip Technology Inc.

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